There is a constant strive in the industry to manufacture ever more compact, fast and energy efficient electronic circuits. To this end much effort has been put into developing methods for fabricating smaller and faster semiconductor devices, inter alia transistors.
In the prior art, field effect transistors (FETs) such as metal-insulator-semiconductors (MISFETs) have been fabricated in so-called gate-first processes wherein the gate is formed over a channel layer before formation of the source and drain regions. The source and drain regions are often formed by a highly doped semiconductor. One advantage of the gate-first process is that it is comparably simple to design the process such that the gate becomes self-aligned to the channel region (i.e. between the source and drain regions) and thus limit the series resistance between the source and drain. One drawback is however that during the formation of the source and drain regions the interface between the gate and the channel layer may be adversely affected by high temperature processing such as ion implantation followed by doping activation anneal, or by regrowth processes performed at elevated temperatures. This must be considered when designing the gate-channel interface and may thus limit the design options. A further drawback specific to doping by ion implantation is that implantation processes not are efficient for all materials. For example, implantation in III/V materials generally results in poor contact material quality.
An alternative process is the so-called gate-last process wherein the source and drain regions are formed before the gate is fabricated on the substrate. Thereby degradation of the gate-channel interface during fabrication of the transistor may be avoided or at least reduced. However, special attention is required when designing the process to ensure that the gate becomes accurately aligned with the channel region.
US 2006/0286755 discloses a gate-last method of fabricating PMOS and NMOS transistors wherein the gate becomes self-aligned. According to the method a dummy gate structure is fabricated on a silicon layer of a SOI substrate. Thereafter the silicon layer is etched such that the etch undercuts the dummy gate structure, thereby achieving a thinning of the channel region. Highly doped source and drain regions are then epitaxially grown on the etched silicon layer on opposite sides of the dummy gate structure. A dielectric layer is deposited over the resulting structure to cover the source region, the drain region and the dummy gate structure. The dielectric layer is planarized in a chemical mechanical polishing (CMP) process to become flush with the top surface of the dummy gate structure. By the deposition of the dielectric layer and the following planarization step the dummy gate structure may thereafter be etched away wherein a trench extending through the dielectric layer may be formed and subsequently filled with a metal gate.
This method however imposes constraints on the design of the gate. In order to enable removal of the dummy gate structure, the dummy structure must be accessible from the surface of the planarized dielectric layer. The height of the gate above the silicon layer is thus restricted by the height of the dummy gate structure. This may render it more difficult to define shorter gate lengths since the minimum aspect ratio of the gate is determined inter alia by the maximum aspect ratio of the dummy gate structure. Moreover the two separate processes of depositing the dielectric layer and planarizing the same which are performed before the gate can be formed adds to the complexity of the method.